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| PRELIMINARY FEBRUARY 2007 XRK32308 3.3V ZERO DELAY BUFFER REV. P1.0.3 GENERAL DESCRIPTION FUNCTIONAL DESCRIPTION XRK32308 is a 3.3V Zero Delay Buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FB pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 350 ps, and output-to-output skew is guaranteed to be less than 200 ps. XRK32308 has two banks of four outputs each. These can be controlled by the Select inputs as shown in Table 2, "Select Input Decoding," on page 2. If all output clocks are not required, Bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. Multiple XRK32308 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. XRK32308 devices are available in five different configurations, as shown in Table 3, "Available XRK32308 Configurations," on page 3. The XRK32308-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The XRK32308-1H is the high-drive version of the - 1. Rise and fall times on this device are faster. The XRK32308-2 allows the user to obtain 1X, and 2X or X/2 depending on which Bank sources the FB signal. The XRK32308-3 allows the user to obtain 4X and 2X frequencies or 1X and 2X. The XRK32308-4 enables the user to obtain 2X clocks on all outputs. The XRK32308-5H is a high-drive version with REF/ 2 on both banks. FEATURES * Zero input-output propagation delay, adjustable by capacitive load on FB input * Multiple configurations, see "Available XRK32308 Configurations" table * Multiple low-skew outputs * Two banks of four outputs, three-stateable by two select inputs * 10-MHz to 120-MHz operating range * 75ps typical cycle-to-cycle jitter (15pF, 66MHz) * Space-saving 16-pin 150-mil SOIC package, 16-pin TSSOP or 16-pin QFN * 3.3V operation * Industrial and commercial temperature available FIGURE 1. BLOCK DIAGRAM AND PIN CONFIGURATION OF THE XRK32308 /2 PLL REF /2 Extra Divider (-3, -4) Extra Divider (-5H) S2 S1 MUX FB QA0 QA1 QA2 QA3 QA0 REF FB QA3 REF QA0 QA1 VDD GND QB0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FB QA3 QA2 VDD GND QB3 QB2 S1 QA1 VDD GND QB0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 QA2 VDD GND QB3 Select Input Decoding /2 QB0 QB1 Extra Divider (-2, -3) QB2 QB3 QB1 S2 QB1 S2 S1 QB2 Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com XRK32308 3.3V ZERO DELAY BUFFER PRELIMINARY REV. P1.0.3 TABLE 1: PIN DESCRIPTION PIN SIGNAL SOIC/TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 QFN 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 REF[1] QA0[2] QA1[2] VDD GND QB0[2] QB1[2] S2[3] S1[3] QB2[2] QB3[2] GND VDD QA2[2] QA3[2] FB Input reference frequency Clock output, Bank A Clock output, Bank A 3.3V supply Ground Clock output, Bank B Clock output, Bank B Select input, bit 2 Select input, bit 1 Clock output, Bank B Clock output, Bank B Ground 3.3V supply Clock output, Bank A Clock output, Bank A PLL feedback input DESCRIPTION TABLE 2: SELECT INPUT DECODING S2 0 0 1 1 NOTES: 1. 2. 3. 4. Weak pull-down. Weak pull-down on all outputs. Weak pull-ups on these inputs. Outputs inverted on XRK32308-2 and XRK32308-3 in bypass mode, S2 = 1 and S1 = 0. S1 0 1 0 1 QA0-QA3 Three-State Driven Driven[4] Driven QB0-QB3 Three-State Three-State Driven[4] Driven OUTPUT SOURCE PLL PLL Reference PLL 2 PRELIMINARY REV. P1.0.3 XRK32308 3.3V ZERO DELAY BUFFER TABLE 3: AVAILABLE XRK32308 CONFIGURATIONS DEVICE XRK32308-1 XRK32308-1H XRK32308-2 XRK32308-2 XRK32308-3 XRK32308-3 XRK32308-4 XRK32308-5H NOTES: 5. Output phase is indeterminant (0 or 180 from input clock). If phase integrity is required, use the XRK32308-2. FEEDBACK FROM Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A or Bank B Bank A or Bank B BANK A FREQUENCY Reference Reference Reference 2 X Reference 2 X Reference 4 X Reference 2 X Reference Reference/2 BANK B FREQUENCY Reference Reference Reference/2 Reference Reference or Reference[5] 2 X Reference 2 X Reference Reference/2 ZERO DELAY AND SKEW CONTROL FIGURE 2. REF INPUT TO QAX/QBX DELAY VS DIFFERENCE IN LOADING BETWEEN FB AND QAX/QBX PINS 1500 1000 REF Input to QAx/QBx Delay (ps) 500 0 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -500 -1000 -1500 Output Load Difference: FB Load - QAx/QBx Load (pF) Note: Target only, actual characterization curve may be slightly different. To close the feedback loop of the XRK32308, the FB pin can be driven from any of the eight available output pins. The output driving the FB pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. This is shown in the graph above. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. 3 XRK32308 3.3V ZERO DELAY BUFFER PRELIMINARY REV. P1.0.3 TABLE 4: ABSOLUTE MAXIMUM RATINGS Supply Voltage to Ground Potential DC Input Voltage (Except Ref) DC Input Voltage REF Storage Temperature Junction Temperature Static Discharge Voltage (per MIL-STD-883, Method 3015) -0.5V to +7.0V -0.5V to V DD +0.5V -0.5 to 7V -65C to +150C 150C >2000V TABLE 5: OPERATING CONDITIONS FOR XRK32308 COMMERCIAL TEMPERATURE DEVICES PARAMETER VDD TA CL Load Capacitance, from 100MHz to 120MHz CIN tPU Input Capacitance[6] Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 15 7 50 pF pF ms Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100MHz DESCRIPTION MIN 3.0 0 MAX 3.6 70 30 UNIT V C pF NOTES: 6. Applies to both Ref Clock and FB. TABLE 6: ELECTRICAL CHARACTERISTICS FOR XRK32308 COMMERCIAL TEMPERATURE DEVICES PARAMETER VIL VIH IIL IIH VOL DESCRIPTION Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage[7] VIN=0V VIN=VDD IOL= 8mA (-1, -2, -3, -4) IOL= 12mA (-1H, -5H) VOH Output High Voltage[7] IOH= -8mA (-1, -2, -3, -4) IOH= -12mA (-1H, -5H) 2.4 V TEST CONDITIONS MIN 2.0 MAX 0.8 50.0 100.0 0.4 UNIT V V A A V 4 PRELIMINARY REV. P1.0.3 XRK32308 3.3V ZERO DELAY BUFFER TABLE 6: ELECTRICAL CHARACTERISTICS FOR XRK32308 COMMERCIAL TEMPERATURE DEVICES PARAMETER DESCRIPTION TEST CONDITIONS Unloaded outputs, 100-MHz REF, Select inputs at VDD or GND MIN MAX 45.0 70 (-1H, -5H) 32.0 18.0 UNIT mA mA mA mA IDD Supply Current Unloaded outputs, 66-MHz REF (-1, -2, -3, -4) Unloaded outputs, 33-MHz REF (-1, -2, -3, -4) NOTES: 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. TABLE 7: SWITCHING CHARACTERISTICS FOR XRK32308 COMMERCIAL TEMPERATURE DEVICES[8] PARAMETER NAME TEST CONDITIONS 30-pF load, All devices t1 Output Frequency 20-pF load, -1H, -5H devices[9] 15-pF load, -1, -2, -3, -4 devices Measured at 1.4V, FOUT=66.66MHz 30-pF load Measured at 1.4V, FOUT<50.0MHz 15-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 15-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 15-pF load Measured between 0.8V and 2.0V, 30-pF load MIN 10 10 10 40.0 TYP 50.0 MAX 100 120 120 60.0 UNIT MHz MHz MHz % DC Duty = t2 / t1 (-1, -2, -3, -4, -1H, -5H) Cycle[7] 45.0 50.0 55.0 % - - 2.20 1.50 1.50 ns ns ns Rise (-1, -2, -3, -4) t3 Rise Time[7] (-1H, -5H) Time[7] - - 2.20 1.50 1.25 ns ns ns Fall (-1, -2, -3, -4) t4 Fall Time[7] (-1H, -5H) Time[7] 5 XRK32308 3.3V ZERO DELAY BUFFER PRELIMINARY REV. P1.0.3 TABLE 7: SWITCHING CHARACTERISTICS FOR XRK32308 COMMERCIAL TEMPERATURE DEVICES[8] PARAMETER NAME TEST CONDITIONS MIN TYP MAX 200 UNIT ps Output to Output Skew on All outputs equally loaded same Bank (-1, -2, -3, -4)[7] Output to Output Skew (-1H, -5H)[7] t5 Output Bank A to Output Bank B Skew (-1, -4, -5H) Output Bank A to Output Bank B Skew (-2, -3) t6 t7 t8 FB Rising Edge[7] Device to Device Skew[7] Output Slew Rate[7] Measured at VDD/2 on the FB pins of devices Measured between 0.8V and 2.0V on -1H, -5H device using Test Circuit #2 Measured at 66.67MHz, loaded outputs, 15-pF load Cycle to Cycle Jitter[7] (-1, -1H, -4, -5H) tJ Measured at 66.67MHz, loaded outputs, 30-pF load Measured at 120MHz, loaded outputs, 15-pF load Measured at 66.67MHz, loaded outputs, 30-pF load Measured at 66.67MHz, loaded outputs, 15-pF load Stable power suppy, valid clock presented on REF and FB pins All outputs equally loaded - - 200 ps All outputs equally loaded - - 200 ps All outputs equally loaded - - 400 ps Delay, REF Rising Edge to Measured at VDD/2 - 0 +250 ps - 0 700 ps 1 - 75 200 200 100 400 400 1.0 V/ns ps ps ps ps ps ms Cycle to Cycle (-2, -3) Jitter[7] tLOCK PLL Lock Time[7] NOTES: 8. 9. All parameters are specified with loaded outputs. XRK32308 has maximum input frequency of 120MHz and maximum output of 66.67MHz. 6 PRELIMINARY REV. P1.0.3 XRK32308 3.3V ZERO DELAY BUFFER TABLE 8: OPERATING CONDITIONS FOR XRK32308 INDUSTRIAL TEMPERATURE DEVICES PARAMETER VDD TA CL Load Capacitance, from 100MHz to 120MHz CIN tPU Input Capacitance[6] Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 15 7 50 pF pF ms Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100MHz DESCRIPTION MIN 3.0 -40 MAX 3.6 85 30 UNIT V C pF TABLE 9: ELECTRICAL CHARACTERISTICS FOR XRK32308 INDUSTRIAL TEMPERATURE DEVICES PARAMETER VIL VIH IIL IIH VOL DESCRIPTION Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage[7] VIN=0V VIN=VDD IOL= 8mA (-1, -2, -3, -4) IOL= 12mA (-1H, -5H) VOH Output High Voltage[7] IOH= -8mA (-1, -2, -3, -4) IOH= -12mA (-1H, -5H) Unloaded outputs, 100 MHz REF, Select inputs at VDD or GND 45.0 70 (-1H, -5H) 35.0 20.0 mA mA mA mA 2.4 V TEST CONDITIONS MIN 2.0 MAX 0.8 50.0 100.0 0.4 UNIT V V A A V IDD Supply Current Unloaded outputs, 66-MHz REF (-1, -2, -3, -4) Unloaded outputs, 33-MHz REF (-1, -2, -3, -4) 7 XRK32308 3.3V ZERO DELAY BUFFER PRELIMINARY REV. P1.0.3 TABLE 10: SWITCHING CHARACTERISTICS FOR XRK32308 INDUSTRIAL TEMPERATURE DEVICES[8] PARAMETER NAME TEST CONDITIONS 30-pF load, All devices t1 Output Frequency 20-pF load, -1H, -5H devices[9] 15-pF load, 01, 02, 03, 04 devices Measured at 1.4V, FOUT=66.66MHz 30-pF load Measured at 1.4V, FOUT<50.0MHz 15-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 15-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 15-pF load Measured between 0.8V and 2.0V, 30-pF load MIN 10 10 10 40.0 TYP 50.0 MAX 100 120 120 60.0 UNIT MHz MHz MHz % DC Duty Cycle = t2 / t1 (-1, -2, -3, -4, -1H, -5H) [7] 45.0 50.0 55.0 % - - 2.5 1.50 1.50 ns ns ns Rise Time[7] (-1, -2, -3, -4) t3 Rise Time[7] (-1H, -5H) - - 2.50 1.50 1.25 ns ns ns Fall Time[7] (-1, -2, -3, -4) t4 Fall Time[7] (-1H, -5H) Output to Output Skew on All outputs equally loaded same Bank (-1, -2, -3, -4)[7] Output to Output Skew (-1H, -5H) t5 Output Bank A to Output Bank B Skew (-1, -4, -5H) Output Bank A to Output Bank B Skew (-2, -3) t6 All outputs equally loaded All outputs equally loaded - - 200 ps - - 200 ps - - 200 ps All outputs equally loaded - - 400 ps Delay, REF Rising Edge to Measured at VDD/2 FB Rising Edge[7] Device to Device Skew[7] Output Slew Rate[7] Measured at VDD/2 on the FB pins of devices Measured between 0.8V and 2.0V on -1H, -5H device using Test Circuit #2 - 0 +250 ps t7 t8 - 0 700 ps 1 - V/ns 8 PRELIMINARY REV. P1.0.3 XRK32308 3.3V ZERO DELAY BUFFER TABLE 10: SWITCHING CHARACTERISTICS FOR XRK32308 INDUSTRIAL TEMPERATURE DEVICES[8] PARAMETER NAME TEST CONDITIONS Measured at 66.67MHz, loaded outputs, 15-pF load Cycle to Cycle Jitter[7] (-1, -1H, -4, -5H) tJ Measured at 66.67MHz, loaded outputs, 30-pF load Measured at 120MHz, loaded outputs, 15-pF load Measured at 66.67MHz, loaded outputs, 30-pF load Measured at 66.67MHz, loaded outputs, 15 pF load Stable power suppy, valid clocks presented on REF and FB pins MIN TYP 75 MAX 200 200 100 400 400 1.0 UNIT ps ps ps ps ps ms Cycle to Cycle Jitter (-2, -3) [7] tLOCK PLL Lock Time[7] FIGURE 3. SWITCHING WAVEFORMS All Outputs Rise/Fall Time Duty Cycle Timing t1 t2 1.4V 1.4V 1.4V OUTPUT 2.0V 0.8V t3 2.0V 0.8V t4 3.3V 0V Output-Output Skew Input-Output Skew OUTPUT OUTPUT 1.4V 1.4V t5 INPUT FB VDD/2 VDD/2 t6 Device-Device Skew FB, Device 1 FB, Device 2 VDD/2 VDD/2 t7 9 XRK32308 3.3V ZERO DELAY BUFFER FIGURE 4. TEST CIRCUIT Test Circuit #1 VDD 0.1F Outputs PRELIMINARY REV. P1.0.3 Test Circuit #2 VDD QAx/QBx CLOAD 0.1F Outputs 1K 1K QAx/QBx 10pF VDD 0.1F GND GND 0.1F VDD GND GND Test Circuit for all parameters except t 8. Test Circuit for t 8. Output slew rate on -1H, -5 device. 10 PRELIMINARY REV. P1.0.3 XRK32308 3.3V ZERO DELAY BUFFER TABLE 11: ORDERING INFORMATION PART ORDERING NUMBER XRK32308CD-1 XRK32308CDTR-1 XRK32308ID-1 XRK32308IDTR-1 XRK32308CL-1 XRK32398IL-1 XRK32308CD-1H XRK32308CDTR-1H XRK32308ID-1H XRK32308IDTR-1H XRK32308CG-1H XRK32308CGTR-1H XRK32308IG-1H XRK32308IGTR-1H XRK32308CL-1H XRK32308IL-1H XRK32308CD-2 XRK32308CDTR-2 XRK32308ID-2 XRK32308IDTR-2 XRK32308CL-2 XRK32308IL-2 XRK32308CD-3 XRK32308CDTR-3 XRK32308ID-3 XRK32308IDTR-3 XRK32308CL-3 XRK32308IL-3 XRK32308CD-4 XRK32308CDTR-4 XRK32308ID-4 XRK32308IDTR-4 PACKAGE TYPE 16 Pin SOIC 16 Pin SOIC 16 Pin SOIC 16 Pin SOIC 16 Pin QFN 16 Pin QFN 16 Pin SOIC 16 Pin SOIC 16 Pin SOIC 16 Pin SOIC 16 Pin TSSOP 16 Pin TSSOP 16 Pin TSSOP 16 Pin TSSOP 16 Pin QFN 16 Pin QFN 16 Pin SOIC 16 Pin SOIC 16 Pin SOIC 16 Pin SOIC 16 Pin QFN 16 Pin QFN 16 Pin SOIC 16 Pin SOIC 16 Pin SOIC 16 Pin SOIC 16 Pin QFN 16 Pin QFN 16 Pin SOIC 16 Pin SOIC 16 Pin SOIC 16 Pin SOIC OPERATING TEMPERATURE RANGE 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 11 XRK32308 3.3V ZERO DELAY BUFFER PRELIMINARY REV. P1.0.3 TABLE 11: ORDERING INFORMATION PART ORDERING NUMBER XRK32308CL-4 XRK32308IL-4 XRK32308CD-5H XRK32308CDTR-5H XRK32308CL-5H XRK32308IL-5H PACKAGE TYPE 16 Pin QFN 16 Pin QFN 16 Pin SOIC 16 Pin SOIC 16 Pin QFN 16 Pin QFN OPERATING TEMPERATURE RANGE 0 to +70 -40 to +85 0 to +70 0 to +70 0 to +70 -40 to +85 12 PRELIMINARY REV. P1.0.3 XRK32308 3.3V ZERO DELAY BUFFER PACKAGE DRAWINGS AND DIMENSIONS 16 LEAD SMALL OUTLINE (150 MIL JEDEC SOIC) rev. 1.00 D 16 1 9 E 8 H C A Seating Plane e B A1 L Note: The control dimension is the millimeter column INCHES SYMBOL A A1 B C D E e H L MIN 0.053 0.004 0.013 0.007 0.386 0.150 MAX 0.069 0.010 0.020 0.010 0.394 0.157 MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 0.050 BSC 0.228 0.016 0 0.244 0.050 8 1.27 BSC 5.80 0.40 0 6.20 1.27 8 13 XRK32308 3.3V ZERO DELAY BUFFER PRELIMINARY REV. P1.0.3 16 LEAD TSSOP THIN SHRINK SMALL OUTLINE (4.4mm TSSOP) Rev. 1.0 SYMBOL A A1 A2 B C D E E1 e L INCHES MIN MAX 0.031 0.043 0.002 0.006 0.031 0.037 0.007 0.012 0.004 0.008 0.193 0.201 0.248 0.260 0.169 0.177 0.0256 BSC 0.018 0.030 0 8 MILLIMETERS MIN MAX 0.80 1.10 0.05 0.15 0.80 0.95 0.19 0.30 0.09 0.20 4.90 5.10 6.30 6.60 4.30 4.50 0.65 BSC 0.45 0.75 0 8 14 PRELIMINARY REV. P1.0.3 XRK32308 3.3V ZERO DELAY BUFFER 16 LEAD QUAD FLAT NO LEAD (4 mm x 4 mm x 0.9mm, 0.65 pitch QFN) Rev. 1.02 Note: the actual center pad is metallic and the size (D2) is device-dependent w/ a typical tolerance of 0.3mm Note: The control dimension is in millimeter. SYMBOL A A1 A3 D D2 b e L INCHES MIN 0.031 0.000 0.000 0.154 0.087 0.010 MAX 0.039 0.002 0.008 0.161 0.102 0.014 MILLIMETERS MIN MAX 0.80 0.00 0.00 3.90 2.20 0.25 1.00 0.05 0.20 4.10 2.60 0.35 0.0256 BSC 0.018 0.026 0.65 BSC 0.45 0.65 15 XRK32308 3.3V ZERO DELAY BUFFER REVISIONS REV. # P1.0.0 P1.0.1 P1.0.2 P1.0.3 DATE 04/05/06 04/21/06 05/12/06 02/01/07 Initial release. PRELIMINARY REV. P1.0.3 DESCRIPTION OF CHANGES Ordering information edit: Added "H" to last two product numbers. Operating range changed to 10MHz to 120MHz - edit all references of this. Add QFN package. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2007 EXAR Corporation Datasheet February 2007. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 16 |
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